CISC

CISC is a self explanatory term that works towards making the instruction more complex in order to reduce the semantic gap lying between the instruction and machine codes. This complex instruction is a sequence of numerous critical operations. And hence number of clock cycles is taken for the execution of one single instruction. The origin of this trend was seen in MINICOMPUTERS in 1970s.

Throughout 1970s, the basic aim of single chip processor designing was to achieve the highest possible number of transistors on a single chip. As a result the manufacturing of processors was done in semiconductor industry, instead of computer industry. Thus we almost overlooked the scope of technological advancement and architectural demands while designing the processors.

Moreover we became highly dependent on MICROCODE ROMs that had complex subroutines stored in them. These MICROCODE ROMs are located in processors only. The basic drawback of these MICROCODE ROMs was that they left a very little scope for the introduction of any other performance enhancing feature, as they covered the majority of space on a single chip processor.

v RISC

The concept of RISC came in 1980 by Patterson and Ditzel which was further supported by Berkely. Berkely gave the design of RISC I over CISC processor which has high performance level. Early RISC projects: IBM 801 (America), Berkeley SPUR, RISC I and RISC II and Stanford MIPS.

Some of the key feature of RISC :-

1. RISC execute a instruction in one cycle and it has a fixed instruction length of 32 bit while in the case of CISC it has variable instruction length of different format and it take several cycle to execute a instruction.

2. In the case of CISC memory location is used as operand in data processing while in RISC there are separate instruction for accessing memory and data in register.

3. In CISC different register had different purpose so even if they were large they could not use all there register. While in RISC any register can be used for any purpose, it only depends on register management.

4. RISC uses Hard-wired instruction decode logic and CISC uses microcode ROM to decode instruction.

5. RISC uses pipelining technique. In pipelining two or more instruction is been executed at a time and this improve the utilization of the hardware resources. A less of pipelining is used in CISC.

6. RISC architecture are simple which enable the programmer to exploit the organization technique. It is able to exploit all its memory units while CISC is not able to use all its memory units.

7. RISC processor cost less in design than CISC, and it has high performance than CISC.

RISC – (MIPS, DEC Alpha, SUN Sparc, IBM 801) & CISC (VAX, Intel X86, IBM 360/370, etc).