Data Alignment and its Significance in ARM

Data alignment refers to the storage of data at a location from where it takes the minimum number of operation cycles for the processor to read the data. The task execution process in a processor is basically divided into two parts; reading/writing the data and processing the data. And generally speaking,reading/writing the data is responsible for the majority portion of the time taken in task execution. Therefore, if data is properly aligned in the memory device then the time taken for the execution of the task is reduced to a great extent. Data alignment basically depends upon the factors like address lines, data lines and number of physical divisions of memory device.

Talking about ARMs, data alignment plays a pivotal role in the execution process. This has been explained in following points.

• ARMs have 32 address lines (A0 to A31).
• It has 32 data lines (D0 to D31).
• The memory of ARM is divided into four layers of 512 kilobytes each (A, B, C and D).
• Among these four memory layers only one is selected and accessed at one time.
• To select a layer out of four we use two address lines; A0 ad A1.

A1 A0 MEMORY LAYER

0 0 A

0 1 B

1 0 C

1 1 D

• A0 and A1 are termed as memory select lines.
• Rest of the address lines (A2 to A31) are connected to four memory layers.
• 32 data lines are connected to 4 memory layers i.e. (D0-D7) to memory layer A, (D8-D15) to memory layer B, (D16-D23) to memory layer C and (D24-D31) is connected to memory layer D.

• Now comes the role of data alignment.
• The concept is that if the processor starts reading the data from the first layer then it will pick 8 bits each from 4 layers in one go or in one operation cycle.
• Here data alignment refers to the storage of first 8 bits of data on layer A.
• Now let us analyze both the cases i.e. when data is aligned and when it is not aligned.

v When data is aligned :

1. Processor has to fetch total 32 bits from memory (8 bits from all four layers).
2. Since the data is aligned therefore first 8 bits of data will be located on layer A, next 8 bits on layer B, third 8 bits on layer C and last 8 bits on layer D.
3. The necessary condition for completing the task in one operation cycle is that the state of address lines from A2 to A31 should remain unchanged. We can change the value of A1 and A0.
4. By keeping the value of A1 A0 = 00 we can read the 8 bits of data from layer A. Next we make A1A0 = 01 we can read the 8 bit data

from layer B. Then we make A1 A0 = 10 we fetch the data from layer C. And we keep A1 A0 = 11 we read the data from layer D.

5. Therefore, complete 32 bits of data is fetched keeping A2 to A31 unchanged.
6. Example :

Let A31 to A0 = 1010101010101001010101010101000

For first 8 bits- layer A-> 1010101010101001010101010101000

For second 8 bits- layer B->1010101010101001010101010101001

For third 8 bits- layer C-> 1010101010101001010101010101010

For forth 8 bits- layer D-> 1010101010101001010101010101011

7. And thus all 32 bits are picked in one operation cycle keeping A2 to A31 unchanged.

v When data is not aligned:

1. In this case data must be kept at any of the three layers apart from layer A.
2. In such a situation, processor has to change the value of A2 to A31 to fetch the data. And hence it will take more than one operation cycle.
3. Example :

Let A31 to A0 = 1010101010101001010101010101010

For first 8 bits- layer C-> 1010101010101001010101010101010

For second 8 bits- layer D->1010101010101001010101010101011

For third 8 bits- layer A-> 1010101010101001010101010101100

For forth 8 bits- layer B-> 1010101010101001010101010101101

4. And since we have to change the state of the A2 bit from 0 to 1therefore, it takes four operation cycles for fetching this data.